QL5432 Datasheet - QuickLogic Corporation

Architecture Overview
The QL5432 device in the QuickLogic QuickPCI Embedded Standard Product (ESP) family provides a complete and customizable PCI interface solution combined with programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus bandwidth (132 MBps).

Device Highlights
High Performance PCI Controller
QL5432 supports new enhanced features added to QL5232:
• All PCI commands (including configuration and MWI)
• Fully-customizable byte enables as a master
• Zero-wait-state write and one-wait-state read Target interface
• Target interface supports retry, disconnect with/without data transfer, and target abort
• Target aborts
• Has 125 more logic cells in FPGA section, but 2 less RAM blocks
• Pin compatible with QL5232
  QL5432 also supports the original features of QL5232:
• 32-bit/33 MHz PCI Master/Target
• Zero-wait state PCI Master provides 132 MBps transfer rates
• Programmable back-end interface to optional local processor
• Independent PCI bus (33 MHz) and local bus (up to 160 MHz) clocks
• Fully customizable PCI configuration space
• Configurable FIFOs with depths up to 256
• Reference design with driver code (Win 95/98/2000/NT4.0) available
• PCI v2.2 compliant
• Supports Type 0 configuration cycles in Target mode
• 3.3 V, 5 V tolerant PCI signaling supports universal PCI adapter designs
• 3.3 V CMOS in 208-pin PQFP and 456-pin PBGA
• Supports endian conversions
• Unlimited/continuous burst transfers supported

Extendable PCI Functionality
• Support for configuration space from 0x40 to 0x3FF
• Multi-function, expanded capabilities, and expansion ROM capable
• Power management, compact PCI, hot swap/hot-plug compatible
• PCI v2.2 Power Management Spec compatible
• PCI v2.2 Vital Product Data (VPD) configuration support

Programmable logic
• 1,417 logic cells
• 23,040 RAM bits, up to 266 I/O pins
• 250 MHz 16-bit counters, 275 MHz Datapaths, 160 MHz FIFOs
• All back-end interface and glue-logic can be implemented on chip
• Any combination of FIFOs that require 20 or less QuickLogic RAM modules
• Six 32-bit busses interface between the PCI Controller and the Programmable Logic