M48Z128V Datasheet - STMicroelectronics

DESCRIPTION
The M48Z128/Y/V ZEROPOWER® RAM is a 128 Kbit x 8 non-volatile static RAM organized as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP module. This solution is available in two special packages to provide a highly integrated battery backed-up memory solution.
   
FEATURES SUMMARY
■ INTEGRATED, ULTRA LOW POWER SRAM,
    POWER-FAIL CONTROL CIRCUIT, and
    BATTERY
■ CONVENTIONAL SRAM OPERATION;
    UNLIMITED WRITE CYCLES
■ 10 YEARS OF DATA RETENTION IN THE
    ABSENCE OF POWER
■ BATTERY INTERNALLY ISOLATED UNTIL
    POWER IS FIRST APPLIED
■ AUTOMATIC POWER-FAIL CHIP DESELECT
    and WRITE PROTECTION
■ WRITE PROTECT VOLTAGES:
    (VPFD = Power-fail Deselect Voltage)
    – M48Z128: VCC = 4.75 to 5.5V
        4.5V ≤ VPFD ≤ 4.75V
    – M48Z128Y: VCC = 4.5 to 5.5V
        4.2V ≤ VPFD ≤ 4.5V
    – M48Z128V: VCC = 3.0 to 3.6V
        2.8V ≤ VPFD ≤ 3.0V
■ SOIC PACKAGE PROVIDES DIRECT
    CONNECTION FOR A SNAPHAT TOP WHICH
    CONTAINS THE BATTERY
■ SNAPHAT HOUSING (BATTERY) IS
    REPLACEABLE
■ PIN and FUNCTION COMPATIBLE WITH
    JEDEC STANDARD 128K x 8 SRAMs
■ EQUIVALENT SURFACE-MOUNT (SMT)
    SOLUTION REQUIRES A 28-PIN M40Z300/W
    and A STAND-ALONE 128K x8 LPSRAM
    (SNAPHAT® Top to be ordered separately)