JS28F512P30TFA Datasheet - Micron Technology

Overview
   P30-65nm device provides high performance on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power-up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register (RCR) enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.

   In addition to the enhanced architecture and interface, the device incorporates technology that enables fast buffer program and erase operations. The device features a 512-word buffer to enable optimum programming performance, which can improve system programming throughput time significantly to 1.46MByte/s.