ICS8543BGLF Datasheet - Integrated Device Technology

General Description
The ICS8543 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The ICS8543 has two selectable clock inputs.

FEATUREs
• Four differential LVDS output pairs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input levels:
   LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK, nPCLK pair can accept the following differential input
   levels: LVPECL, CML, SSTL
• Maximum output frequency: 800MHz
• Translates any single-ended input signals to LVDS levels with
   resistor bias on nCLK input
• Additive phase jitter, RMS: 0.164ps (typical)
• Output skew: 40ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 2.6ns (maximum)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
   packages