FC106 Datasheet - STMicroelectronics

General Description
The FC106 Fibre Channel transceiver chip implements the lower layer protocols of the ANSI X3.230-1994 Fibre Channel standard. The Fibre Channel standard specifies the mapping of various upper layer protocols (ULP) such as SCSI, IP and HiPPI to a common lower layer protocol, together with appropriate electrical and optical high performance specifications. Fibre Channel provides a channel over which concurrent communication of a variety of ULP’s may exist on a single interconnect between workstations, mainframes and supercomputers, and provides a connection to mass storage devices and other peripherals.

FEATURES
■ Serial Link Transceiver
   ● serializer and deserializer
   ● implementing the Fibre Channel FC0 and FC1 layers
■ Direct support for 1.0625 GBaud Fibre Channel (ANSI X3.230-1994) rates
■ Fibre Channel 10-bit Interface (ANSI TR/X3.18-199X)
■ Direct interfaces to optical tranceivers
■ Plesiochronous mode operation
● transmitter and receiver clock
   frequencies may differ by up to 100 ppm
■ Integrated Fibre Channel 8b/10b
   encode/decode (optional use through JTAG)
■ Byte and word synchronization of incoming serial stream
■ Supports any DC-balanced encoding scheme
■ Internal Loop-Back for Self-Test
■ Random Pattern Auto-Test
■ Optional integrated impedance
   adaptation to transmission line characteristics (50 or 75 ohms)
■ TTL compatible parallel I/O’s
■ JTAG Test Access Port
■ 0.35µ CMOS Technology for low cost and low power
■ PQFP package available in two sizes:
   14x14 mm (FC106/14) or 10x10 mm (FC106/10)

APPLICATIONS
■ Fibre Channel Arbitrated Loop
■ Fibre Channel fabric
■ Transmission schemes encoding
   bytes as 10-bit characters to form a DC-balanced stream
■ High performance backplane interconnect