DSPIC33FJ16MC102-E/SP Datasheet - Microchip Technology

Operating Conditions
• 3.0V to 3.6V, -40°C to +125°C, DC to 16 MIPS
• 3.0V to 3.6V, -40°C to +150°C, DC to 5 MIPS

Core: 16-Bit dsPIC33F CPU
• Code-Efficient (C and Assembly) Architecture
• Two 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL plus Hardware Divide
• 32-Bit Multiply Support

Clock Management
• ±0.25% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast Wake-up and Start-up

Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 1 mA/MHz Dynamic Current (typical)
• 30 µA IPD Current (typical)

PWM
• Up to Three PWM Pairs
• Two Dead-Time Generators
• 31.25 ns PWM Resolution
• PWM Support for:
   - Inverters, PFC, UPS
   - BLDC, PMSM, ACIM, SRM
• Class B-Compliant Fault Inputs
• Possibility of ADC Synchronization with PWM Signal

Advanced Analog Features
• ADC module:
   - 10-bit, 1.1 Msps with four S&H
   - Four analog inputs on 18-pin devices and up to
   14 analog inputs on 44-pin devices
• Flexible and Independent ADC Trigger Sources
• Three Comparator modules
• Charge Time Measurement Unit (CTMU):
   - Supports mTouch™ capacitive touch sensing
   - Provides high-resolution time measurement (1 ns)
   - On-chip temperature measurement

Timers/Output Compare/Input Capture
• Up to Five General Purpose Timers:
   - One 16-bit and up to two 32-bit timers/counters
• Two Output Compare modules
• Three Input Capture modules
• Peripheral Pin Select (PPS) to allow Function Remap