AS8C801825A Datasheet - Alliance Semiconductor

Description
   The 803625A/801825A are 3.3V high-speed 9,437,184-bit (9 Megabit) synchronous SRAMs organized as 256K x 36/512K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround.

FEATUREs
◾ 256K x 36, 512K x 18 memory configuration
◾ Supports high performance system speed –
   100MHz (7.5ns Clock-To-Data Access)
◾ ZBTTM Feature – No dead cycles between write
   and read cycles
◾ Internally synchronized output buffer enable
   eliminates the need to control OE
◾ Single R/W (READ/WRITE) control pin
◾ 4-word burst capability (Interleaved or linear)
◾ Individual byte write (BW1 – BW4) control
   (May tie active)
◾ Three chip enables for simple depth expansion
◾ 3.3V power supply (±5%)
◾ 3.3V (±5%) I/O Supply (VDDQ)
◾ Power down controlled by ZZ input
◾ Packaged in a JEDEC standard 100-pin plastic
   thin quad flatpack (TQFP)