CS493105 View Datasheet(PDF) - Cirrus Logic
Part Name
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MFG CO.
CS493105 Datasheet PDF : 90 Pages
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CS49300 Family DSP
significant bit set to 1 to designate a read.
4) After the falling edge of the serial control clock
(SCCLK) for the read/write bit, the data is ready
to be clocked out on the control data out pin
(CDOUT). Data clocked out by the host is valid
on the rising edge of SCCLK and data
transitions occur on the falling edge of SCCLK.
The serial clock should be default low so that
eight transitions from low to high to low will
occur for each byte.
5) If INTREQ is still low, another byte should be
clocked out of the CS493XX. Please see the
discussion below for a complete description of
INTREQ behavior.
6) When INTREQ has risen, the chip select line of
the CS493XX should be raised to end the read
transaction.
Understanding the role of INTREQ is important for
successful communication. INTREQ is guaranteed
to remain low (once it has gone low) until the
second to last rising edge of SCCLK of the last byte
to be transferred out of the CS493XX. If there is no
more data to be transferred, INTREQ will go high
at this point. For SPI this is the rising edge for the
second to last bit of the last byte to be transferred.
After going high, INTREQ is guaranteed to stay
high until the next rising edge of SCCLK. This end
of transfer condition signals the host to end the
read transaction by clocking the last data bit out
and raising CS. If INTREQ is still low after the
second to last rising edge of SCCLK, the host
should continue reading data from the serial
control port.
It should be noted that all data should be read out
of the serial control port during one cycle or a loss
of data will occur. In other words, all data should be
read out of the chip until INTREQ signals the last
byte by going high as described above. Please see
Section 6.1.3, “INTREQ Behavior: A Special Case”
on page 41 for a more detailed description of
INTREQ behavior.
Figure 21, "SPI Timing" on page 39 timing diagram
shows the relative edges of the control lines for an
SPI read and write.
6.1.2. I2C Communication
I2C communication with the CS493XX is
accomplished with 3 communication lines: serial
control clock, a bi-directional serial data
input/output line and an interrupt request line to
signal that the DSP has data to transmit to the host.
See Figure 4, "I2C® Communication Signals" on
page 38 shows the mnemonic, pin name, and pin
number of each of these signals on the CS493XX.
Mnemonic
Serial Clock
Pin Name Pin Number
SCCLK
7
Bi-Directional Data
SCDIO
19
Interrupt Request
INTREQ
20
Table 4. I2C® Communication Signals
Typically in I2C® communication SCDIO is an open
drain line with a pull-up. A logic one is placed on
the line by three-stating the output and allowing the
pull-up to raise the line. At this point another device
can drive the line low if necessary. Three-stating
SCDIO can have two effects: 1. To send out a one
when writing data or sending a “no acknowledge”;
2. release the line when another chip is writing
data.
6.1.2.1. Writing in I2C®
When writing to the device in I2C® the same
protocol will be used whether writing a byte, a
message or even an application code image. The
examples shown in this document can be
expanded to fit any write situation. Figure 23
shows a typical write sequence:
The following is a detailed description of an I2C®
write sequence with the CS493XX.
1) An I2C® transfer is initiated with an I2C® start
condition which is defined as the data (SCDIO)
line falling while the clock (SCCLK) is held
high.
2) Next a 7-bit address with the read/write bit set
low for a write should be sent to the CS493XX.
The address for the CS493XX defaults to
0000000b. It is necessary to clock this address
in prior to any transfer in order for the
CS493XX to accept the write. In other words a
byte of 0x00 should be clocked into the device
38
DS339F7
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