CS493105 View Datasheet(PDF) - Cirrus Logic
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MFG CO.
CS493105 Datasheet PDF : 90 Pages
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CS49300 Family DSP
6. CONTROL
Control of the CS493XX can be accomplished
through one of four methods. The CS493XX
supports I2C® and SPI serial communication. In
addition the CS493XX supports both a Motorola
and Intel byte wide parallel host control mode. Only
one of the four communication modes can be
selected for control. The states of the RD, WR, and
PSEL pins are sampled at the rising edge of
RESET to determine the interface type as shown in
Table 2.
RD
(Pin 5)
1
1
0
1
WR
(Pin 4)
1
1
1
0
PSEL
(Pin 19)
1
0
X
X
Host Interface Mode
8-bit Motorola®
8-bit Intel®
Serial I2C®
Serial SPI
Table 2. Host Modes
Whichever host communication mode is used, host
control of the CS493XX is handled through the
application software running on the DSP.
Configuration and control of the CS493XX decoder
and its peripherals are indirectly executed through
a messaging protocol supported by the
downloaded application code. In other words
successful communication can only be
accomplished by following the low level hardware
communication format and high level messaging
protocol. The specifications of the messaging
protocol can be found in any of the software user’s
guides.
Only the subsection describing the communication
mode being used needs to be read by the system
designer.
6.1. Serial Communication
The CS493XX has a serial control port that
supports both SPI and I2C® forms of
communication.
The following sections will explain each
communication mode in more detail. Flow
diagrams will illustrate read and write cycles.
Timing diagrams will be shown to demonstrate
relative edge positions of signal transitions for read
and write operations.
6.1.1. SPI Communication
SPI communication with the CS493XX is
accomplished with 5 communication lines: chip
select, serial control clock, serial data in, serial
data out and an interrupt request line to signal that
the DSP has data to transmit to the host. Table 3
shows the mnemonic, pin name, and pin number of
each of these signals on the CS493XX.
Mnemonic
Pin Name Pin Number
Chip Select
CS
18
Serial Clock
SCCLK
7
Serial Data In
SCDIN
6
Serial Data Out
SCDOUT
19
Interrupt Request INTREQ
20
Table 3. SPI Communication Signals
6.1.1.1. Writing in SPI
When writing to the device in SPI the same
protocol will be used whether writing a byte, a
message or even an entire executable download
image. The examples shown in this document can
be expanded to fit any write situation. Figure 19,
"SPI Write Flow Diagram" on page 37 shows a
typical write sequence:
The following is a detailed description of an SPI
write sequence with the CS493XX.
1) An SPI transfer is initiated when chip select
(CS) is driven low.
2) This is followed by a 7-bit address and the
read/write bit set low for a write. The address
for the CS493XX defaults to 0000000b. It is
necessary to clock this address in prior to any
transfer in order for the CS493XX to accept the
write. In other words a byte of 0x00 should be
clocked into the device preceding any write.
The 0x00 byte represents the 7 bit address
0000000b, and the least significant bit set to 0
to designate a write.
3) The host should then clock data into the device
most significant bit first, one byte at a time. The
data byte is transferred to the DSP on the
falling edge of the eighth serial clock. For this
reason, the serial clock should be default low
so that eight transitions from low to high to low
will occur for each byte.
36
DS339F7
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