CS8900-CQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

mal processing. That exception can occur when

when the hash-filter Broadcast address matches a

bit in the Logical Address Filter. To properly ac-

count for this exception, the software driver

should use the following test to determine if the

RxEvent register contains a normal RxEvent

(meaning bits E-A are used for Extra data, Runt,

CRC Error, Broadcast and IndividualAdr) or a

hash-table RxEvent (meaning bits F-A contain

the Hash Table Index).

If

bit Hashed =0, or

bit RxOK=0, or

(bits F-A = 02h and the destination

address is all ones)

then RxEvent contains a normal RxEvent

else RxEvent contained a hash RxEvent.

5.4 Receive DMA

5.4.1 Overview

The CS8900 supports a direct interface to the

host DMA controller allowing it to transfer re-

ceive frames to host memory via slave DMA.

The DMA option applies only to receive frames,

and not transmit operation. The CS8900 offers

three possible Receive DMA modes:

PacketPage

Address

Register Description

0024h

DMA Channel Number: DMA channel

number (0, 1, or 2) that defines the

DMARQ/DMACK pin pair used.

0026h

DMA Start of Frame: 16-bit value that

defines the offset from the DMA base

address to the start of the most recently

transferred received frame.

0028h

DMA Frame Count: The lower 12 bits

define the number of valid frames

transferred via DMA since the last read-out

of this register. The upper 4 bits are

reserved and not applicable.

002Ah

DMA Byte Count: Defines the number of

bytes that have been transferred via DMA

since the last read-out of this register.

Table 5.8. Receive DMA Registers

DS150PP2

1. Receive-DMA-only mode: All receive frames

are transferred via DMA.

2. Auto-Switch DMA: DMA is used only when

needed to help prevent missed frames.

3. StreamTransfer: DMA is used to minimize

the number of interrupts to the host.

This section provides a description of Receive-

DMA-only mode. Section 5.5 describes

Auto-Switch DMA and Section 5.6 describes

StreamTransfer.

5.4.2 Configuring the CS8900 for DMA

Operation

The CS8900 interfaces to the host DMA control-

ler through one pair of the DMA

request/acknowledge pins (see Section 3.2 for a

description of the CS8900’s DMA interface).

Four 16-bit registers are used for DMA opera-

tion. These are described in Table 5.8.

Receive-DMA-only mode is enabled by setting

the RxDMAonly bit (Register 3, RxCFG, Bit 9).

Note: If the RxDMAonly bit and the AutoRxD-

MAE bit (Register 3, RxCFG, Bit A) are both

set, then RxDMAonly takes precedence, and the

CS8900 is in DMA mode for all receive frames.

5.4.3 DMA Receive Buffer Size

In receive DMA mode, the CS8900 stores re-

ceived frames (along with their status and length)

in a circular buffer located in host memory

space. The size of the circular buffer is deter-

mined by the RxDMAsize bit (Register 17,

BusCTL, Bit D). When RxDMAsize is clear, the

buffer size is 16 Kbytes. When RxDMAsize is

set, the buffer is 64 Kbytes. It is the host’s task

to locate and keep track of the DMA receive

buffer’s base address. The DMA Start-of-Frame

register is the only circuit affected by this bit.

89

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