CS8900-CQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8900-CQ Datasheet PDF : 132 Pages
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CS8900
IAHashA
0
1
0
0
X
PromiscuousA
0
0
0
0
1
MulticastA
0
IndividualA
1
BroadcastA
0
0
0
0
1
0
0
0
0
1
X
X
X
Table 5.6. DA Filtering Options
Frames Accepted
Individual Address frames
with DA matching the IA at
PacketPage base + 0158h
Individual Address frames
with DA that pass the hash
filter (DA[0] must be "0")
Multicast frames with DA
that pass the hash filter
(DA[0] must be "1")
Broadcast frames
All frames
For example, if MulticastA and IndividualA are
set, then all frames that are either Multicast or
Individual Address frames are accepted. The
PromiscuousA bit, when set, overrides the other
four DA bits, and allows all valid frames to be
accepted. Table 5.6 summarizes the configuration
options available for DA filtering.
It may become necessary for the host to change
the Destination Address (DA) filter criteria with-
out resetting the CS8900. This can be done as
follows:
1. Clear SerRxON (Register 13, LineCTL, Bit 6)
to prevent any additional receive frames while
the filter is being changed.
2. Modify the DA filter bits (B, A, 9, 7, and 6) in
the RxCTL register.
Modify the Logical Address Filter at Packet-
Page base + 0150h, if necessary.
Modify the Individual Address at PacketPage
base + 0158h, if necessary.
3. Set SerRxON to re-enable the receiver.
Because the receiver has been disabled, the
CS8900 will ignore frames while the host is
changing the DA filter.
Hash Filter
The hash filter is used to help determine which
Multicast frames and which Individual Address
frames should be accepted by the CS8900.
Hash Filter Operation: See Figure 5.5. The DA
of the incoming frame is passed through the
CRC logic, generating a 32-bit CRC value. The
six most-significant bits of the CRC are latched
into the 6-bit hash register (HR). The contents of
the HR are passed through a 6-to-64-bit decoder,
asserting one of the decoder’s outputs. The as-
serted output is compared with a corresponding
bit in the 64-bit Logical Address Filter, located at
PacketPage base + 0150h. If the decoder output
and the Logical Address Filter bit match, the
frame passes the hash filter and the Hashed bit
(Register 4, RxEvent, Bit 9) is set. If the two do
not match, the frame fails the filter and the
Hashed bit is clear.
Whenever the hash filter is passed by a "good"
frame, the RxOK bit (Register 4, RxEvent, Bit 8)
is set and the bits in the HR are mapped to the
Hash Table Index bits (Register 4, RxEvent, Bits
A through F).
Broadcast Frame Hashing Exception
DS150PP2
Table 5.7 describes in detail the content of the
RxEvent register for each output of the hash and
address filters, and describes an exception to nor-
87
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