CS8900 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Register 10: Receiver Miss Counter (RxMISS, Read-only)

Address: PacketPage base + 0130h

F-6

MissCount

5-0

010000

The RxMISS counter (Bits 6 through F) records the number of receive frames that are lost (missed) due to the

lack of available buffer space. If the MissOvfloiE bit (Register B, BufCFG, Bit D) is set, there is an interrupt when

RxMISS increments from 1FFh to 200h. This interrupt provides the host with an early warning that the RxMISS

counter should be read before it reaches 3FFh and starts over (by interrupting at 200h, the host has an addi-

tional 512 counts before RxMISS actually overflows). The RxMISS counter is cleared when read.

BIT NAME

DESCRIPTION

5-0 010000

These bits provide an internal address used by the CS8900 to identify this as the Bus

Status Register. When reading this register, these bits will be 010000, where the LSB

corresponds to Bit 0.

F-6 MissCount

The upper ten bits contain the number of missed frames.

This register’s initial state after reset is: 0000 0000 0001 0000

58

DS150PP2

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