CS8900 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8900 Datasheet PDF : 132 Pages
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CS8900
Register C: Buffer Event (BufEvent, Read-only)
Address: PacketPage base + 012Ch
F
E
D
C
B
A
9
8
7
RxDest
Rx128
RxMiss TxUnder Rdy4Tx RxDMA
run
Frame
BufEvent gives the status of the transmit and receive buffers.
6
SWint
5-0
001100
BIT NAME
DESCRIPTION
5-0 001100
These bits provide an internal address used by the CS8900 to identify this as the Buffer
Event Register. When reading this register, these bits will be 001100, where the LSB
corresponds to Bit 0.
6
SWint
If set, there has been a software initiated interrupt. This bit is used in conjunction with
the SWint-X bit (Register B, BufCFG, Bit 6).
7
RxDMAFrame If set, one or more received frames have been transferred by slave DMA. If RxDMAiE
(Register B, BufCFG, Bit 7) is set, there is an interrupt.
8
Rdy4Tx
If set, the CS8900 is ready to accept a frame from the host for transmission. If
Rdy4TxiE (Register B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 5.7 for a
description of the transmit bid process.)
9
TxUnderrun This bit is set if CS8900 runs out of data before it reaches the end of the frame (called
a transmit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an
interrupt.
A
RxMiss
If set, one or more receive frames have been lost due to slow movement of data out of
the receive buffers. If RxMissiE (Register B, BufCFG, Bit A) is set, there is an interrupt.
B
Rx128
This bit is set after the first 128 bytes of an incoming frame have been received. This bit
will allow the host the option of pre-processing frame data before the entire frame is
received. If Rx128iE (Register B, BufCFG, Bit B) is set, there is an interrupt.
F
RxDest
When set, this bit shows that a receive frame has passed the Destination Address Filter
criteria as defined in the RxCTL register (Register 5). This bit is useful as an early
indication of an incoming frame. It will be earlier than Rx128 (Register C, BufEvent, Bit
B). If RxDestiE (Register B, BufCFG, Bit F) is set, there is an interrupt.
This register’s initial state after reset is: 0000 0000 0000 1100
NOTE:
With any event register, like BufEvent, all bits are cleared upon readout. The host is responsible for
processing all event bits.
DS150PP2
57
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