CS8900-CQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8900-CQ Datasheet PDF : 132 Pages
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CS8900
Register 4: Receiver Event (RxEvent, Read-only)
Address: PacketPage base + 0124h
F
E
D
C
B
A
9
8
7
6
5-0
Extradata Runt
CRCerror Broadcast Individ
ualAdr
Hashed
RxOK Dribblebits IAHash 000100
Alternate meaning if bits 8 and 9 are both set (see Section 5.3 for exception regarding Broadcast frames).
F
E
D
C
B
A
9
8
7
6
5-0
Hash Table Index (see Section 5.3)
Hashed RxOK= 1 Dribblebits IAHash
=1
000100
RxEvent reports the status of the current received frame. All RxEvent bits are cleared upon readout. The host is
responsible for processing all event bits. RxStatus register (PacketPage base + 0400h) is the same as the
RxEvent register except RxStatus is not cleared when RxEvent is read. See Section 5.2.
BIT NAME
DESCRIPTION
5-0 000100
These bits identify this as the Receiver Event Register. When reading this register, these
bits will be 000100, where the LSB corresponds to Bit 0.
6
IAHash
If the received frame’s Destination Address is accepted by the hash filter, then this bit is
set if, and only if, RxOK (Bit 8) is set, IAHashA (Register 5, RxCTL, Bit 6) is set, and
Hashed (Bit 9) is set. See Section 5.3.
7
Dribblebits
If set, the received frame had from one to seven bits after the last received full byte. An
"Alignment Error" occurs when Dribblebits and CRCerror (Bit C) are both set.
8
RxOK
If set, the received frame had a good CRC and valid length (i.e., there is not a CRC
error, Runt error, or Extradata error). When RxOK is set, then the length of the received
frame is contained at PacketPage base + 0402h. If RxOKiE (Register 3, RxCFG, Bit 8)
is set, there is an interrupt.
9
Hashed
If set, the received frame had a Destination Address that was accepted by the hash
filter. If Hashed and RxOK (Bit 8) are set, Bits F through A of RxEvent become the
Hash Table Index for this frame [See Section 5.3 for an exception regarding broadcast
frames!]. If Hashed and RxOK are not both set, then Bits F through A are individual
event bits as defined below.
A
IndividualAdr If the received frame had a Destination Address which matched the Individual Address
found at PacketPage base + 0158h, then this bit is set if, and only if, RxOK (Bit 8) is set
and IndividualA (Register 5, RxCTL, Bit A) is set.
B
Broadcast
If the received frame had a Broadcast Address (FFFF FFFF FFFFh) as the Destination
Address, then this bit is set if, and only if, RxOK is set and BroadcastA (Register 5,
RxCTL, Bit B) is set.
C CRCerror
If set, the received frame had a bad CRC. If CRCerroriE (Register 3, RxCFG, Bit C) is
set, there is an interrupt.
D Runt
If set, the received frame was shorter than 64 bytes. If RuntiE (Register 3, RxCFG, Bit
D) is set, there is an interrupt.
E
Extradata
If set, the received frame was longer than 1518 bytes. All bytes beyond 1518 are
discarded. If ExtradataiE (Register 3, RxCFG, Bit E) is set, there is an interrupt.
This register’s initial state after reset is: 0000 0000 0000 0100
50
DS150PP2
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