CS8900-CQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

4.4 Status and Control Registers

The Status and Control registers are the primary

registers used to control and status the CS8900.

They are organized into two groups: Configura-

tion/Control Registers and Status/Event

Registers. All Status and Control Registers are

16-bit words as shown in Figure 4.1. Bit 0 indi-

cates whether it is a Configuration/Control

Register (Bit 0 = 1) or a Status/Event Register

(Bit 0 = 0). Bits 0 through 5 provide an internal

address code that describes the exact function of

the register. Bits 6 through F are the actual Con-

figuration/Control and Status/Event bits.

These registers are read/write and are designated

by odd numbers (e.g. Register 1, Register 3,

etc.).

The Transmit Command Register (TxCMD) is a

special type of register. It appears in two separate

locations in the PacketPage memory map. The

first location, PacketPage base + 0108h, is within

the block of Configuration/Control Registers and

is read-only. The second location, PacketPage

base + 0144h, is where the actual transmit com-

mands are issued and is write-only. See Section

4.4 (Register 9) and Section 5.7 for a more de-

tailed description of the TxCMD register.

Configuration and Control Registers

Status and Event Registers

Configuration and Control registers are used to

setup the following:

• how frames will be transmitted and received;

• which frames will be transmitted and re-

ceived;

• which events will cause interrupts to the

host processor; and,

• how the Ethernet physical interface will be

configured.

Status and Event registers report the status of

transmitted and received frames, as well as infor-

mation about the configuration of the CS8900.

They are read-only and are designated by even

numbers (e.g. Register 2, Register 4, etc.).

The Interrupt Status Queue (ISQ) is a special

type of Status/Event register. It is located at

PacketPage base + 0120h and is the first register

the host reads when responding to an Interrupt.

A more detailed description of the ISQ can be

found in Section 5.1.

16-bit Register Word

Bit Number

F EDCBA9 8 7 6 5 4 3 2 1 0

Internal Address

(bits 0 - 5)

1 = Control/Configuration

0 = Status/Event

10 Register Bits

Figure 4.1. Status and Control Register Format

44

DS150PP2

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