CS8900-CQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Bus Interface Register:

Interrupt Number (Read/Write)

Address 0023h

00h

Address: PacketPage base + 0022h

Address 0022h

Interrupt number assignment:

0000 0000b= pin INTRQ0

0000 0001b= pin INTRQ1

0000 0010b= pin INTRQ2

0000 0011b= pin INTRQ3

0000 01XXb= All INTRQ pins high-impedance

The Interrupt Number Register defines the interrupt pin selected by the CS8900. In a typical application the

following bus signals are tied to the following pins:

Bus signal

Typical pin connection

IRQ5

INTRQ3

IRQ10

INTRQ0

IRQ11

INTRQ1

See Section 3.2.

IRQ12

INTRQ2

After reset, if no EEPROM is found by the CS8900, then the register has the following initial state, which

corresponds to placing all the INTRQ pins in a high-impedance state. If an EEPROM is found, then the register’s

initial value may be set by the EEPROM. See Section 3.3.

XXXX XXXX XXXX X100

Bus Interface Register:

DMA Channel Number (Read/Write)

Address 0025h

00h

Address: PacketPage base + 0024h

Address 0024h

DMA channel assignment:

0000 0000b = pins DMRQ0 and DMACK0

0000 0001b = pins DMRQ1 and DMACK1

0000 0010b = pins DMRQ2 and DMACK2

0000 01XXb = All INTRQ pins high-impedance

The DMA Channel register defines the DMA pins selected by the CS8900. In the typical application, the follow-

ing bus signals are tied to the following pins:

Bus signal

Typical pin connection

DRQ5

DACK5

DMRQ0

DMACK0

DRQ6

DACK6

DMRQ1

DMACK1

DRQ7

DACK7

DMRQ2

DMACK2

See Sections 3.2 and 5.4.

After reset, if no EEPROM is found by the CS8900, then the register has the following initial state which corre-

sponds to selecting pins DMRQ0 and DMACK0. If a EEPROM is found, then the register’s initial value may be

set by the EEPROM. See Section 3.3.

XXXX XXXX XXXX XX11

DS150PP2

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