AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

AT89C51CC03C-RLTIM

Enhanced 8-bit MCU with CAN Controller and Flash Memory

Atmel Corporation 

Power Down Request

Reading the Flash Spaces

User

Extra Row

Hardware Security Byte

Before entering in Power Down (Set bit PD in PCON register) the user should check that

no write sequence is in progress (check BUSY=0), then check that the column latches

are reset (FLOAD=0 in FSTA register. Launch a reset column latches to clear FLOAD if

necessary.

The following procedure is used to read the User space:

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with

A+DPTR=read@.

Note: FCON is supposed to be reset when not needed.

The following procedure is used to read the Extra Row space and is summarized in

Figure 28:

• Map the Extra Row space by writing 02h in FCON register.

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and

DPTR = FF80h to FFFFh.

• Clear FCON to unmap the Extra Row.

The following procedure is used to read the Hardware Security space and is

summarized in Figure 28:

• Map the Hardware Security space by writing 04h in FCON register.

• Read the byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and

DPTR = 0000h.

Figure 28. Clear FCON to unmap the Hardware Security Byte.Reading Procedure

Flash Spaces Reading

Flash Spaces Mapping

FCON= 00000xx0b

Data Read

DPTR= Address

ACC= 0

Exec: MOVC A, @A+DPTR

Clear Mode

FCON = 00h

Flash Protection from Parallel The three lock bits in Hardware Security Byte (see "In-System Programming" section)

Programming

are programmed according to Table 17 provide different level of protection for the on-

chip code and data located in FM0 and FM1.

The only way to write this bits are the parallel mode. They are set by default to level 4

54 AT89C51CC03

4182K–CAN–05/06

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