AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

AT89C51CC03C-RLTIM

Enhanced 8-bit MCU with CAN Controller and Flash Memory

Atmel Corporation 

Overview of FM0

Operations

Flash Registers (SFR)

FCON Register

AT89C51CC03

The CPU interfaces to the flash memory through the FCON register, AUXR1 register

and FSTA register.

These registers are used to map the column latches, HSB, extra row and EEDATA in

the working data or code space.

Table 13. FCON Register

FCON Register (S:D1h)

Flash Control Register

7

FPL3

6

FPL2

5

FPL1

4

FPL0

3

2

1

0

FPS

FMOD1

FMOD0

FBUSY

Bit

Bit

Number Mnemonic Description

Programming Launch Command Bits

7-4

FPL3:0 Write 5Xh followed by AXh to launch the programming according to FMOD1:0.

(see Table 16.)

Flash Map Program Space

When this bit is set:

3

FPS The MOVX @DPTR, A instruction writes in the columns latches space

When this bit is cleared:

The MOVX @DPTR, A instruction writes in the regular XDATA memory space

2-1

FMOD1:0

Flash Mode

See Table 16.

Flash Busy

0

FBUSY

Set by hardware when programming is in progress.

Clear by hardware when programming is done.

Can not be changed by software.

Reset Value= 0000 0000b

47

4182K–CAN–05/06

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