Figure 11. External Data Read Waveforms
CPU Clock
ALE
RD#1
P0
P2 P2
DPL or Ri
D7:0
DPH or P22
Notes: 1. RD# signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
Figure 12. External Data Write Waveforms
CPU Clock
ALE
WR#1
P0
P2 P2
DPL or Ri
D7:0
DPH or P22
Notes: 1. WR# signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
26 AT89C51CC03
4182K–CAN–05/06