AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

AT89C51CC03C-RLTIM

Enhanced 8-bit MCU with CAN Controller and Flash Memory

Atmel Corporation 

Registers

AT89C51CC03

Table 48. CANGCON Register

CANGCON (S:ABh)

CAN General Control Register

7

ABRQ

6

OVRQ

5

4

3

2

TTC

SYNCTTC AUTOBAUD TEST

1

ENA

0

GRES

Bit

Number Bit Mnemonic Description

Abort Request

Not an auto-resetable bit. A reset of the ENCH bit (message object control

7

ABRQ and DLC register) is done for each message object. The pending transmission

communications are immediately aborted but the on-going communication will

be terminated normally, setting the appropriate status flags, TXOK or RXOK.

Overload frame request (initiator)

Auto-resetable bit.

6

OVRQ Set to send an overload frame after the next received message.

Cleared by the hardware at the beginning of transmission of the overload

frame.

Network in Timer Trigger Communication

5

TTC

set to select node in TTC.

clear to disable TTC features.

Synchronization of TTC

When this bit is set the TTC timer is caught on the last bit of the End Of

4

SYNCTTC Frame.

When this bit is clear the TTC timer is caught on the Start Of Frame.

This bit is only used in the TTC mode.

AUTOBAUD

3

AUTOBAUD Set to activate listening mode.

Clear to disable listening mode

2

TEST

Test mode. The test mode is intended for factory testing and not for customer

use.

Enable/Standby CAN Controller

When this bit is set, it enables the CAN controller and its input clock.

When this bit is clear, the on-going communication is terminated normally and

the CAN controller state of the machine is frozen (the ENCH bit of each

1

ENA/STB

message object does not change).

In the standby mode, the transmitter constantly provides a recessive level; the

receiver is not activated and the input clock is stopped in the CAN controller.

During the disable mode, the registers and the mailbox remain accessible.

Note that two clock periods are needed to start the CAN controller state of the

machine.

General Reset (software reset)

0

GRES Auto-resetable bit. This reset command is ‘ORed’ with the hardware reset in

order to reset the controller. After a reset, the controller is disabled.

Reset Value = 0000 0x00b

4182K–CAN–05/06

107

Share Link: