C8051F521-C-IM View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F521-C-IM Datasheet PDF : 221 Pages
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C8051F52x/F53x
Table 2.2. Global DC Electrical Characteristics
–40 to +125 °C, 25 MHz System Clock unless otherwise specified. Typical values are given at 25 °C
Parameter
Conditions
Min Typ Max Units
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
Idle IDD3,4
VDD = 2.1 V:
Clock = 32 kHz
Clock = 200 kHz
Clock = 1 MHz
Clock = 25 MHz
VDD = 2.6 V:
Clock = 32 kHz
Clock = 200 kHz
Clock = 1 MHz
Clock = 25 MHz
—
8
—
22
— 0.09
— 2.2
—
9
—
30
— 0.13
—
3
Idle IDD Frequency Sensitivity3,6
Digital Supply Current3
T = 25 °C:
VDD = 2.1 V, F < 1 MHz
VDD = 2.1 V, F > 1 MHz
VDD = 2.6 V, F < 1 MHz
VDD = 2.6 V, F > 1 MHz
Oscillator not running,
—
90
—
90
— 118
— 118
(Stop or Suspend Mode)
VDD Monitor Disabled.
T = 25 °C
—
2
T = 60 °C
—
3
T = 125 °C
—
50
—
µA
—
µA
—
mA
5
mA
—
µA
—
µA
—
mA
6.5 mA
— µA/MHz
— µA/MHz
— µA/MHz
— µA/MHz
—
µA
—
µA
—
µA
Notes:
1. For more information on VREGIN characteristics, see Table 2.6 on page 30.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on device characterization data; Not production tested.
4. Does not include internal oscillator or internal regulator supply current.
5. IDD can be estimated for frequencies <= 12 MHz by multiplying the frequency of interest by the frequency
sensitivity number for that range. When using these numbers to estimate IDD > 12 MHz, the estimate should be
the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For
example: VDD = 2.6 V; F= 20 MHz, IDD = 7.3 mA – (25 MHz – 20 MHz) x 0.184 mA/MHz = 6.38 mA.
6. Idle IDD can be estimated for frequencies <= 1 MHz by multiplying the frequency of interest by the frequency
sensitivity number for that range. When using these numbers to estimate IDD > 1 MHz, the estimate should be
the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For
example: VDD = 2.6 V; F= 5 MHz, Idle IDD = 3 mA – (25 MHz– 5 MHz) x 118 µA/MHz = 0.64 mA.
Rev. 1.4
27
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