
17.1.3 SPI1DAT1 - 0x06, 0x07, 0x08
CS5376
Figure 68. SPI 1 Data Register SPI1DAT1
(MSB) 23
S1DAT23
R/W
0
22
S1DAT22
R/W
0
21
S1DAT21
R/W
0
20
S1DAT20
R/W
0
19
S1DAT19
R/W
0
18
S1DAT18
R/W
0
17
S1DAT17
R/W
0
16
S1DAT16
R/W
0
15
S1DAT15
R/W
0
14
S1DAT14
R/W
0
13
S1DAT13
R/W
0
12
S1DAT12
R/W
0
11
S1DAT11
R/W
0
10
S1DAT10
R/W
0
9
S1DAT9
R/W
0
8
S1DAT8
R/W
0
7
S1DAT7
R/W
0
6
S1DAT6
R/W
0
5
S1DAT5
R/W
0
4
S1DAT4
R/W
0
3
S1DAT3
R/W
0
2
S1DAT2
R/W
0
1
S1DAT1
R/W
0
(LSB) 0
S1DAT0
R/W
0
SPI 1 Address: 0x06
0x07
0x08
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable and
Writable
Bits in bottom rows
are reset condition
Bit definitions:
23:16 S1DAT[23:16] SPI 1 Data 1 High 15:8 S1DAT[15:8] SPI 1 Data 1 Middle 15:8 S1DAT[7:0] SPI 1 Data 1 Low
Byte
Byte
Byte
DS256PP1
97