CS5376-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

SWITCHING CHARACTERISTICS Notes:TA = -40 °C to +85 °C; VD = 3.0 V ± 5% or 5.0 V ± 5%;

VDD1 = 3.3 V ± 5% or 5.0 V ± 5%; VDD2 = 3.3 V ± 5% or 5.0 V ± 5%; GND = GND1 = GND2 = 0 V; Logic Levels:

Logic 0 = 0 V, Logic 1 = VD, VDD1, VDD2; CL = 50pF

Parameter

Symbol Min

Typ

Max Unit

Master Clock Frequency

(Note 1) CLK

0.1 32.768 33

MHz

Master Clock Duty Cycle

40

-

60

%

Rise Times

Any Digital Input Except SCK (Note 2) trise

-

SCK

-

-

1.0

µs

-

100

µs

Any Digital Output

-

50

-

ns

Fall Times

Any Digital Input Except SCK (Note 2) tfall

SCK

Any Digital Output

-

-

1.0

µs

-

-

100

µs

-

50

-

ns

Modulator Data Interface

MSYNC Setup Time to MCLK rising

tmss

-20

-

-

ns

MCLK rising to Valid MDATA

tmdv

-

-40

75

ns

MSYNC falling to MCLK rising

tmsf

-20

-

-

ns

Serial Port Timing in SPI Slave Mode

Serial Clock Frequency

SCK

-

-

4.096 MHz

Serial Clock

Pulse Width High

t1

Pulse Width Low

t2

100

-

100

-

-

ns

-

ns

Notes: 1. Master clock frequencies below 32.768 MHz will affect generated clock frequencies.

2. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

DS256PP1

6

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