CS5376-BS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5376-BS Datasheet PDF : 122 Pages
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CS5376
coefficients are [1, 4, 6, 4, 1], and the frequency do-
main model is [(sin x)/x]4.
Stage 2 of Sinc2 can be modeled as a 4th order sinc
filter with a decimate by 3 output. The time domain
coefficients are [1, 4, 6, 4, 1], and the frequency do-
main model is [(sin x)/x]4.
Stage 3 of Sinc2 can be modeled as a 4th order sinc
filter with a decimate by 2 output. The time domain
coefficients are [1, 4, 6, 4, 1], and the frequency do-
main model is [(sin x)/x]4.
Stage 4 of Sinc2 can be modeled as a 5th order sinc
filter with a decimate by 2 output. The time domain
coefficients are [1, 5, 10, 10, 5, 1], and the frequen-
cy domain model is [(sin x)/x]5.
Sinc Filter Output Configuration - FSEL Bits = 0x00
Output
Word Rate
4 kHz
DEC Bits
Setting
0x07
Input Bit
Rate1
512 kHz
Sinc1
Decimation
8
Sinc2
Decimation
16
Sinc2
Stages
1,3,4,5
Sinc
Output
4 kHz
FIR1 Filter Output Configuration - FSEL Bits = 0x01
Output
Word Rate
4 kHz
2 kHz
1 kHz
500 Hz
333.3 Hz
250 Hz
DEC Bits
Setting
0x07
0x06
0x05
0x04
0x03
0x02
Input Bit
Rate1
512 kHz
512 kHz
512 kHz
512 kHz
512 kHz
512 kHz
Sinc1
Decimation
8
8
8
8
8
8
Sinc2
Decimation
4
8
16
8
12
16
Sinc2
Stages
4,5
3,4,5
1,3,4,5
3,4,5
2,4,5
1,3,4,5
Sinc
Output
16 kHz
8 kHz
4 kHz
8 kHz
5.33 kHz
4 kHz
FIR2 Filter, IIR Filter Output Configurations - FSEL Bits = 0x02, 0x03, 0x04, 0x05
Output
Word Rate
DEC Bits
Setting
Input Bit
Rate1
Sinc1
Sinc2
Decimation Decimation
Sinc2
Stages
4 kHz
0x07
512 kHz
8
2
5
2 kHz
0x06
512 kHz
8
4
4,5
1 kHz
0x05
512 kHz
8
8
3,4,5
500 Hz
0x04
512 kHz
8
16
1,3,4,5
333.3 Hz
0x03
512 kHz
8
12
2,4,5
250 Hz
0x02
512 kHz
8
8
3,4,5
125 Hz
0x01
512 kHz
8
16
1,3,4,5
62.5 Hz
0x00
512 kHz
8
16
1,3,4,5
1A 256 kHz input rate is oversampled to match the 512 kHz settings.
Figure 37. Sinc Filter Configurations
Sinc
Output
32 kHz
16 kHz
8 kHz
4 kHz
5.33 kHz
8 kHz
4 kHz
4 kHz
DS256PP1
59
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