CS5503-BS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5503-BS Datasheet PDF : 54 Pages
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CDB5501 CDB5503
CDB5501/CDB5503
P-1
CLKIN Source to CS5501/CS5503
INT CLK On-Board 4.9152 MHz OSC
EXT CLK +5 CMOS CLKIN BNC
CLKIN Rate Selection (CLK/2n) with INT CLK on P1 selected.
CLK = 4.9152 MHz
P-2
CLKIN Rate
0
4.9152 MHz
1
2.4576 MHz
2
1.2288 MHz
3
614.4 kHz
4
307.2 kHz
5
153.6 kHz+
6
76.8 kHz+
7
38.4 kHz* +
* Exceeds CLKIN Specifications of CS5501.
+ Exceeds CLKIN specifications of CS5503.
Table 1. Clock Generator
case, the counter divides the input clock by 2n
where n = 0, 1, …7. Any of the binary sub-multi-
ples of the counter input clock can be input to the
CS5501/CS5503 by jumper selection on connec-
tor P2.
The CS5501/CS5503 contains its own on-chip os-
cillator which needs only an external crystal to
function. Ceramic resonators can be used as well
although ceramic resonators and low frequency
crystals will require loading capacitors for proper
operation.
To test the oscillator of the CS5501/CS5503 with
a crystal (Y2) a jumper wire near crystal Y2 must
be opened and another jumper wire soldered into
the appropriate holes provided to connect the
crystal to the chip. Additional holes are provided
on the board for loading capacitors.
Data Output from the CS5501/CS5503
The CS5501 has three available data output
modes (The CS5503 has two available data out-
put modes). The operating mode of the part is
determined by the input voltage level to the
MODE (pin 1) pin of the device. Once a mode is
selected, four other pins on the device are in-
volved in data output. The first of these is the
DRDY pin (pin 18). It is an output from the chip
which signals whenever a new data word is avail-
able in the internal output register of the
CS5501/CS5503. Data can then be read from the
register, but only when the CS pin (pin 16) is
low.
When CS is low, data bits are output in serial
form on the SDATA pin (pin 20). In the Syn-
chronous Self-Clocking mode of the
CS5501/CS5503, the chip provides an output data
clock from the SCLK pin (pin 19). This output
clock is synchronous with the output data and can
be used to clock the data into an external register.
In Synchronous External-Clocking and Asynchro-
nous Communications modes of the CS5501, the
SCLK pin is an input for an external clock which
determines the rate at which data bits appear at
the SDATA output pin. In the CS5503, only syn-
chronous external-clocking mode is available.
The signals necessary for reading data from the
CS5501/CS5503 are all available on connector
P10 as shown in Figure 2.
P-5
SSC
SEC
AC*
Data Output Mode
Synchronous Self-Clocking
Synchronous External-Clocking
Asynchronous Communications
* Available in CS5501 only.
Table 2. Data Output Mode
DS31DB43
45
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