CS5503-BS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5503-BS Datasheet PDF : 54 Pages
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CDB5501 CDB5503
CDB5501/CDB5503
RS-232 Port (for CS5501 only)
Jumper Selections
The CS5501 has a data output mode in which it
formats the data to be UART compatible; each
serial output byte is preceded by a start bit and
terminated with two stop bits. Serial data in this
format is commonly transferred using the RS-232
data interface. Therefore the evaluation board in-
cludes an RS-232 driver and output connector.
The CS5503 does not provide this output mode.
Micro Port
The CS5501/CS5503 was designed to be compat-
ible with many micro-controllers. Therefore the
evaluation board provides access to all of the data
output pins and the control pins of the
CS5501/CS5503 on header connectors.
DIP Switch and CAL Pushbutton
Although all of the control lines to the
CS5501/CS5503 are available on header connec-
tors at the edge of the board, it is preferable to not
require software control of all of these pins.
Therefore DIP switch control is provided on some
of these control lines. The CAL input to the
CS5501/CS5503 is made available at a header pin
for remote control, but pushbutton control of CAL
is also provided.
The evaluation board has many jumper selectable
options. This table describes the jumper selections
available.
P1 Selects between the on-board 4.9152 MHz
oscillator (INT) or an external (EXT) clock
source as the input to the clock generator/
divider chain.
P2 Allows any of the counter/divider output
clock rates to be selected as the input clock
to the CS5501/CS5503.
P3 Allows selection of baud rate clocks when
the CS5501 is in the UART compatible mode.
When using the on-board 4.9152 MHz stand-
ard baud rates between 1200 and 19,200 are
available.
P4 Selects the divide ratio of the Decimation
Counter.
P5 Selects one of the three available output data
modes of the CS5501 or one of two available
output data modes of the CS5503.
P9 Enables the output of the Decimation
Counter to control the CS line of the
CS5501/CS5503.
P11 Connects the baud clock from the on-board
clock divider as the input to the SCLK pin
of the CS5501/CS5503.
R1
10 M
1
U1A 3
2
4.9152 MHz
74HC00 TP1 P1
5
6 INTCLK
4 U1B
R2
5.1 k
EXTCLK
Y1
C1
30 pF
C2
30 pF
CLKIN
TP2
R3
200
V+
C3
0.1 µF
14
12
11
U1C
13
7
TP3
10
V+
CL
U2
16
11 R
74HC4040
C5
8
0.1 µF
1 2 3 4 5 6 7 8 9 10 11 12
9 7 6 5 3 2 4 13 12 14 15 1
P2
P3
9
8
10 U1D
N = 0 1 2 3 4 5 6 7 8 9 10 11 12
Master Clock
TP4
TP5
Baud Clock
BRCLK (fig. 2)
CLKIN (fig. 2)
Figure 1. Clock Generator
DS31DB43
43
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