AD7872JRZ-REEL View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7872JRZ-REEL Datasheet PDF : 24 Pages
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Data Sheet
AD7871/AD7872
MODE 2 INTERFACE
The second interface mode is achieved by hard wiring
CONVST low and the conversion is initiated by taking CS low
while HBEN is low. The track-and-hold amplifier goes into the
hold mode on the falling edge of CS. In this mode, the BUSY/
INT pin assumes its BUSY function. BUSY goes low at the start
of the conversion, stays low during the conversion and returns
high when the conversion is complete. It is normally used in
parallel interfaces to drive the microprocessor into a wait state
for the duration of conversion.
Figure 16 shows the Mode 2 timing diagram for the 14-bit
parallel data output format (14/8/CLK = 5 V). In this case, the
ADC behaves like slow memory. The major advantage of this
interface is that it allows the microprocessor to start the
conversion, wait and then read data with a single read
instruction. The user does not have to worry about servicing
interrupts or ensuring that software delays are long enough to
avoid the reading during conversion.
The Mode 2 timing diagram for byte and serial data is shown in
Figure 17. For 2-byte data read, the lower byte (DB0 to DB7)
has to be accessed first because HBEN must be low to start the
conversion. The ADC behaves like slow memory for this first
read, but the second read to access the upper byte of data is a
normal read. Operation to the serial functions is identical
between Mode 1 and Mode 2. The timing diagram of Figure 17
shows SCLK going into three-state or running continuously
(dashed line).
CS
t15
RD
BUSY
DATA
TRACK-AND-HOLD
GOES INTO HOLD
t18
tCONVERT
t16
TRACK-AND-HOLD RETURNS TO TRACK.
SIGNAL ACQUISITION BEGINS.
THREE-STATE
t7
t17
VALID
DATA
DB13 TO DB0
Figure 16. Mode 2 Timing Diagram, 14-Bit Parallel Read
HBEN1
t19
CS
t15
TRACK-AND-HOLD
GOES INTO HOLD
t20
t18
RD
BUSY
DATA
t16
THREE-STATE
tCONVERT
TRACK-AND-HOLD RETURNS TO TRACK.
SIGNAL ACQUISITION BEGINS
t17
t7
VALID
DATA
DB7 TO DB0
SSTRB2
SCLK3
SDATA2
t10
t11
t13
t12
LEADING
ZEROS
DB13 DB12 DB11 DB10
SERIAL DATA
t14
DB0
t3
t7
t6
VALID
DATA
DB13 TO DB8
1TIMES t15, t18, t19, t8, AND t20 ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
2EXTERNAL 4.7kΩ PULL-UP RESISTOR.
3CONTINUOUS SCLK (DASHED LINE) WHEN 14/8/CLK (CONTROL) = –5V; NONCONTINUOUS WHEN 14/8/CLK (CONTROL) = 0V. EXTERNAL 2kΩ PULL-UP RESISTOR.
Figure 17. Mode 2 Timing Diagram, Byte or Serial Read
Rev. E | Page 13 of 24
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