A Microchip Technology Company
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
ADDRESS AMS-0
CE#
OE#
WE#
DQ6 and DQ2
TCE
TOEH
TOE
Note: AMS = Most significant address
AMS = A19
Figure 10:Toggle Bits Timing Diagram
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
1380 F07.0
ADDRESSES
SIX-BYTE CODE FOR CHIP-ERASE
555
2AA
555
555
2AA
555
TSCE
CE#
OE#
WE#
RY/BY#
TOEH
TBY
TBR
DQ15-0
XXAA XX55
XX80 XXAA XX55
XX10
VALID
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
WP# must be held in proper logic state (VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
1380 F31.0
Figure 11:WE# Controlled Chip-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
23
DS-25018A
05/11