RTL8111C-VB-GR View Datasheet(PDF) - Realtek Semiconductor

Part Name

Description

MFG CO.

RTL8111C-VB-GR

INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS™ APPLICATIONS

Realtek Semiconductor 

6.9.2.

Bits

15

14

13:11

10:00

RTL8111C

Datasheet

Message Control

Table 16. Message Control

RW

Field

Description

RW

MSI-X Enable If 1 and the MSI Enable bit in the MSI Message Control register is 0, the

function is permitted to use MSI-X to request service and is prohibited from

using its INTx# pin. System configuration software sets this bit to enable

MSI-X. A device driver is prohibited from writing this bit to mask a

function’s service request.

If 0, the function is prohibited from using MSI-X to request service.

This bit’s state after reset is 0 (MSI-X is disabled).

This bit is read/write.

RW

Function Mask If 1, all of the vectors associated with the function are masked, regardless of

their per-vector Mask bit states.

If 0, each vector’s Mask bit determines whether the vector is masked or not.

Setting or clearing the MSI-X Function Mask bit has no effect on the state of

the per-vector Mask bits. This bit’s state after reset is 0 (unmasked).

This bit is read/write.

RO

Reserved

Always Returns 0 on a Read. A write operation has no effect.

RO

Table Size

System software reads this field to determine the MSI-X Table Size N, which

is encoded as N-1. The RTL8111C value is ‘00000000001’, indicating a table

size of 2.

6.9.3.

Bits

31:03

02:00

Table Offset/BIR

Table 17. Table Offset/BIR

RW

Field

Description

RW

Table Offset Used as an offset from the address contained by one of the function’s Base

Address registers to point to the base of the MSI-X Table. The lower 3 BIR bits

are masked off (set to zero) by software to form a 32bit QWORD-aligned offset.

This field is read only.

RO

BIR

Indicates which one of a function’s Base Address registers, located beginning at

10h in Configuration Space, is used to map the function’s MSI-X Table into

Memory Space.

BIR Value

Base Address Register

0

10h

1

14h

2

18h

3

1Ch

4

20h

5

24h

6

Reserved

7

Reserved

For a 64-bit Base Address register, the BIR indicates the lower DWORD. With

PCI-to-PCI bridges, BIR values 2 through 5 are also reserved. The function’s

Base Address registers of RTL8111C located beginning at 20h.

This field is read only.

Integrated Gigabit Ethernet Controller for PCI Express

21

Track ID: JATR-1076-21 Rev. 1.5

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