CS42L56 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS42L56

Ultralow Power, Stereo Codec with Class H Headphone Amp

Cirrus Logic 

6.6.2

CS42L56

Clock Ratio

Configures the appropriate internal MCLK divide ratio for LRCK and SCLK.

RATIO[4:0]

01000

01001

01011

01100

01101

10000

10001

10011

10100

10101

11000

11001

11011

11100

11101

Application:

MCLK/LRCK Ratio

128

125

136

192

187.5

256

250

272

384

375

512

500

544

750

768

“Serial Port Clocking” on page 47

MCLK/SCLK Ratio

2

2

2

3

3

4

4

4

6

6

8

8

8

12

12

Notes:

1. Register settings not shown in the table are reserved. Use Table 3. “Serial Port Clock Ratio Settings”

beginning on page 47 for determining the register settings based on the system master clock (MCLK),

bit clock (SCLK) and frame clock (LRCK) frequencies.

6.7 Serial Format (Address 07h)

7

6

5

4

3

2

1

0

Reserved

Reserved

Reserved

Reserved

DIF

Reserved

Reserved

Reserved

6.7.1 CODEC Digital Interface Format

Configures the digital interface format for data on SDOUT and SDIN.

DIF

0

1

Application:

CODEC Interface Format

I²S

Left Justified

DS851F2

61

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