STM8S105K4T3TR(2015) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STM8S105K4T3TR
(Rev.:2015)
(Rev.:2015)
STMicroelectronics
STM8S105K4T3TR Datasheet PDF : 121 Pages
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STM8S105x4/6
Option byte
Table 11. Option byte (continued)
Addr.
Option
name
Option
byte
no.
7
6
5
Option bits
4
3
2
1
Factory
default
0
setting
0x487E
0x487F
Bootloader
OPTBL
NOPTBL
BL[7:0]
NBL[7:0]
0x00
0xFF
Option byte no.
OPT0
OPT1
OPT2
Table 12. Option byte description
Description
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03: Page 0 to 4 defined as UBC, memory write-protected
...
0x3E: Pages 0 to 63 defined as UBC, memory write-protected
Other values: Reserved
Note: Refer to the family reference manual (RM0016) section on Flash write
protection for more details.
AFR[7:0]
Refer to the following table for the description of the alternate function
remapping description of bits [7:2].
OPT3
HSITRIM: High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
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