CS5490-ISZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5490-ISZR Datasheet PDF : 56 Pages
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CS5490
6.6.12 Interrupt Status (Status0) – Page 0, Address 23
23
DRDY
15
-
7
-
22
CRDY
14
POR
6
VSAG
21
WOF
13
-
5
TUP
20
-
12
IOR
4
FUP
19
18
17
-
MIPS
-
11
10
9
-
VOR
-
3
2
1
IC
RX_CSUM_ERR
-
16
VSWELL
8
IOC
0
RX_TO
Default = 0x 00 0000
The Status0 register indicates a variety of conditions within the chip.
Writing a one to a Status0 register bit will clear that bit. Writing a zero to any bit has no effect.
DRDY
Data Ready. During conversion, this bit indicates that low-rate results have been updated.
It indicates completion of other host instruction and the reset sequence.
CRDY
Conversion Ready. Indicates that sample rate (output word rate) results have been updat-
ed.
WOF
Watchdog timer overflow.
[20:19]
Reserved.
MIPS
MIPS overflow.
Sets when the calculation engine has not completed processing a sample before the next
one arrives.
[17]
Reserved.
VSWELL
Voltage channel swell event detected.
[15]
Reserved.
POR
Power out of range. Sets when the measured power would cause the P register to overflow.
[13]
Reserved.
IOR
Current out of range. Set when the measured current would cause the I register to overflow.
[11]
Reserved.
VOR
Voltage out of range. Set when the measured voltage would cause the V register to over-
flow.
[7]
Reserved.
IOC
I Overcurrent.
[9]
Reserved.
VSAG
Voltage channel sag event detected.
TUP
Temperature updated. Indicates when the Temperature register (T) has been updated.
FUP
Frequency updated. Indicates the Epsilon register has been updated.
IC
Invalid command has been received.
RX_CSUM_ERR Received data checksum error. Sets to one automatically if checksum error is detected on
serial port received data.
RX_TO
SDI/RX time out. Sets to one automatically when SDI/RX time out occurs.
38
DS982F2
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