PC48F2000P0VBQ0 View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
PC48F2000P0VBQ0 Datasheet PDF : 102 Pages
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1-Gbit P30 Family
Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 2 of 2)
Num
Symbol
Parameter
Speed
Min
Max
Unit
Notes
R101
R102
tAVVH
tELVH
Address setup to ADV# high
CE# low to ADV# high
R103
tVLQV
ADV# low to output valid
R104
tVLVH
R105
tVHVL
R106
tVHAX
R108
tAPA
R111
tphvh
Clock Specifications
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
RST# high to ADV# high
10
-
ns
10
-
ns
Vcc = 1.8 V – 2.0 V
-
85
ns
1
Vcc = 1.7 V – 2.0 V
-
88
10
-
ns
10
-
ns
9
-
ns
1,4
-
25
ns
1
30
-
ns
R200
fCLK
CLK frequency
R201
tCLK
CLK period
R202
tCH/CL
CLK high/low time
R203
tFCLK/RCLK
CLK fall/rise time
Synchronous Specifications
-
40
MHz
25
-
ns
1,3,6
5
-
ns
-
3
ns
R301
tAVCH/L
Address setup to CLK
9
-
ns
R302
R303
tVLCH/L
tELCH/L
ADV# low setup to CLK
CE# low setup to CLK
9
-
ns
1
9
-
ns
R304
tCHQV / tCLQV CLK to output valid
-
20
ns
R305
tCHQX
Output hold from CLK
3
-
ns
1,5
R306
tCHAX
Address hold from CLK
10
-
ns
1,4,5
R307
tCHTV
CLK to WAIT valid
-
20
ns
1,5
R311
tCHVL
CLK Valid to ADV# Setup
3
-
ns
1
R312
tCHTX
WAIT Hold from CLK
3
-
ns
1,5
NOTES:
1.
See Figure 13, “AC Input/Output Reference Waveform” on page 33 for timing measurements and max allowable input
slew rate.
2.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3.
Sampled, not 100% tested.
4.
Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5.
Applies only to subsequent synchronous reads.
6.
See your local Intel representative for designs requiring higher than 40 MHz synchronous operation.
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
37
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