PC48F2000P0ZBQ0 View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
PC48F2000P0ZBQ0 Datasheet PDF : 102 Pages
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7.3
AC Read Specifications
1-Gbit P30 Family
Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Asynchronous Specifications
R1
tAVAV
Read cycle time
R2
tAVQV
Address to output valid
R3
tELQV
CE# low to output valid
R4
tGLQV
OE# low to output valid
R5
tPHQV
RST# high to output valid
R6
tELQX
CE# low to output in low-Z
R7
tGLQX
OE# low to output in low-Z
R8
tEHQZ
CE# high to output in high-Z
R9
tGHQZ
OE# high to output in high-Z
R10
tOH
Output hold from first occurring address, CE#, or OE# change
R11
tEHEL
CE# pulse width high
R12
tELTV
CE# low to WAIT valid
R13
tEHTZ
CE# high to WAIT high-Z
R15
tGLTV
OE# low to WAIT valid
R16
tGLTX
OE# low to WAIT in low-Z
R17
tGHTZ
OE# high to WAIT in high-Z
Latching Specifications
R101
tAVVH
R102
tELVH
R103
tVLQV
R104
tVLVH
R105
tVHVL
R106
tVHAX
R108
tAPA
R111
tphvh
Clock Specifications
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
RST# high to ADV# high
R200
fCLK
CLK frequency
R201
tCLK
CLK period
R202
tCH/CL
CLK high/low time
R203
tFCLK/RCLK
CLK fall/rise time
Synchronous Specifications
R301
R302
R303
R304
tAVCH/L
tVLCH/L
tELCH/L
tCHQV / tCLQV
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
85
-
-
85
-
85
-
25
-
150
0
-
0
-
-
24
-
24
0
-
20
-
-
17
-
20
-
17
0
-
-
20
10
-
10
-
-
85
10
-
10
-
9
-
-
25
30
-
-
40
25
-
5
-
-
3
9
-
9
-
9
-
-
20
Unit
Notes
ns
ns
ns
ns
1,2
ns
1
ns
1,3
ns
1,2,3
ns
ns
1,3
ns
ns
1
ns
ns
1,3
ns
1
ns
1,3
ns
ns
ns
ns
1
ns
ns
ns
1,4
ns
1
ns
MHz
ns
ns
ns
1,3,6
ns
ns
1
ns
ns
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
35
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