7.0
AC Characteristics
1-Gbit P30 Family
7.1
AC Test Conditions
Figure 13.
Figure 14.
AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
Note: AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends
at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin.
Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
.
Table 14.
NOTES:
1.
See the following table for component values.
2.
Test configuration component value for worst case speed conditions.
3.
CL includes jig capacitance
Test configuration component value for worst case speed conditions
Test Configuration
VCCQMin Standard Test
CL (pF)
30
Figure 15. Clock Input AC Waveform
VIH
CLK [C]
VIL
R202
R201
R203
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
33