CL-PS7110 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7110

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7110

Low-Power System-on-a-Chip

4.6.7 Software-Selectable Test Functionality

When bit 11 of the SYSCON register is set HIGH, all internal EPB accesses are output on the main

address and data buses as though they were external accesses to the address space addressed by CS6.

Hence CS6 handles a dual role: It is active as the strobe for internal accesses and for any accesses to

the standard address range for CS6. Additionally in this mode, the following internal signals are multi-

plexed out of the device on port pins:

Signal

NIRQ

NFIQ

I/O

Pin

Function

O

PE1

NIRQ interrupt to CPU

O

PE2

NFIQ interrupt to CPU

NOTE: Port E defaults to input so PE1 and PE2 has to be programmed to output mode to observe NIRQ and NFIQ

on these signals.

74

ELECTRICAL SPECIFICATIONS

May 1997

DATA BOOK v1.5

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