CL-PS7110 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7110

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7110

Low-Power System-on-a-Chip

Within each test mode a selection of pins are used as multiplexed outputs or inputs to provide/monitor the

test signals unique to that mode.

4.6.1 Oscillator and PLL Bypass Mode

This mode is selected by NTEST0 = 1, NTEST1 = 0.

In this mode all the internal oscillators and PLL are disabled and the appropriate crystal oscillator pins

become the direct external oscillator inputs bypassing the oscillator and PLL. MOSCIN must be driven by

a 36.864-MHz clock source and RTCOUT by a 32.768-kHz source. In addition the OSCEN (oscillator

enable) signal is multiplexed out on Port C bit 0 to control the external oscillator. It is driven logic to level

low to disable the oscillator. The functionality of the CL-PS7110 is not affected in any other way during

this test mode.

4.6.2 Functional (EPB) Test Mode

This mode is selected by NTEST0 = 0, NTEST1 = 1, Latched NURESET = 1

Functional EPB (embedded peripheral bus) Test mode is used for the running test patterns, both through

the EPB external test interface and for any other patterns. It is for testing individual peripherals and the

ARM710A microprocessor. The PLL is automatically bypassed in this mode. In this mode various pins are

used as control inputs or outputs; these are listed in Table 4-5.

Table 4-5. EPB Test Mode Signal Assignment

Signal

TSTA

TSTB

TSTSTART

TSTDIRCLK

TSTVCOUNT

TACK

I/O

Pin Function

I

PA0 EPB test control A

I

PA1 EPB test control B

I

PA2 Fast start speed up RTC divider chain

I

PA3 Insertion point for EPB test clock

I

PA4 Video Address counter increments faster

O

word EPB test acknowledge output

4.6.3 Oscillator and PLL Test Mode

This mode is selected by NTEST0 = 0, NTEST1 = 1, Latched NURESET = 0

This test mode enables the main oscillator and output various buffered clock and test signals derived from

the main oscillator, PLL, and 32-kHz oscillator. All internal logic in the CL-PS7110 is static and isolated

from the oscillators with the exception of the 6-bit ripple counter used to generate 576-kHz and the real-

time clock divide chain. Port A is used to drive the inputs of the PLL directly and the various clock and PLL

outputs are monitored on the COL pins. Table 4-6 defines the CL-PS7110 signal pins used in this test

mode.

May 1997

DATA BOOK v1.5

71

ELECTRICAL SPECIFICATIONS

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