CL-PS7110
Low-Power System-on-a-Chip
Figure 1-4 shows the usage of such memory segments.
× 16
FLASH
× 16
ROM
CL-PS7110
D[0:31]
A[0:27]
NMOE
NMWE
NCS0
NCS1
× 16
FLASH
× 16
ROM
CS6
CS7
EXTERNAL MEMORY
MAPPED EXPANSION
BUFFERS
ADDITIONAL I/O
BUFFERS
AND
LATCHES
NCS2
NCS3
Figure 1-4. Memory Segment Usage
The width of each the ROM/expansion bank is set in its Memory Configuration Register 1 (see
Section 3.2.13). This register is cleared to zero by a power-on reset. The CL-PS7110 boots from
ROM/expansion bank 0. To allow for booting from 8- or 32-bit memory devices, the state of port E bit 0 is
sampled during power-on reset and stored into the BOOT8BIT Mode register. If this bit is low, all zeros in
the width field of a memory configuration register indicates a 32-bit-wide bank and all ones a 8-bit device.
If this bit is high, the decoding of the bus width field is inverted, so all zeros indicates a 8-bit device.This
way, a pull-up or pull-down on port E bit 0 indicates the size of the boot device. For consistency, the
BOOT8BIT Mode has the same effect on all ROM/expansion banks.
The PCMCIA mode is a special case. If the width field of the Memory Configuration Register 1 is set to
PCMCIA mode, the upper address bits are decoded to determine the bus width and type of access. The
PCMCIA address bits A0 to A25 are driven by CL-PS7110 address bits A0 to A25. CL-PS7110 address
bits A26 and A27 are decoded to specify the type and width of the access. If both are zeros, it is an access
to the 8-bit-wide attribute memory. If only A26 is a one, it is an access to the 16-bit-wide common memory.
If only A27 is a one, it is an access to a 8-bit-wide I/O register. If both are ones, it is an access to a 16-bit-
wide I/O register.
The ARM710A core only supports byte or word accesses. Normally, word accesses are converted to mul-
tiple bus cycles that match the width of the ROM/expansion bank. Word accesses to PCMCIA 16-bit-wide
18
FUNCTIONAL DESCRIPTION
May 1997
DATA BOOK v1.5