CL-PS7110 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CL-PS7110 Datasheet PDF : 82 Pages
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CL-PS7110
Low-Power System-on-a-Chip
word accesses are produced by cache line fetches and block data transfer instructions. They can be con-
sidered a burst of word reads.
Reads
For byte reads, the CL-PS7110 will rotate the data if needed so that, regardless of the width of the mem-
ory bank, the addressed byte is in the correct position. The remaining bytes will be filled with zeros. Nor-
mally, word accesses to non-word aligned addresses cause an alignment fault. However, if the alignment
fault check in the MMU is not enabled, a word read from an address offset from a word boundary will
cause the data to be rotated into the register as if it were a byte read. Half-word aligned reads will place
the data in correct bytes of the register. Two shift operations are then required to zero-fill or sign extend
the data.
Writes
During byte writes, the data is replicated on each of the four bytes of the data bus. For DRAM writes, there
is CAS line per byte and only the CAS for the correct byte is enabled. For writes to byte-wide ROM/expan-
sion banks, the nMWE signal is directly used as the write enable. For writable 16-bit ROM/expansion
banks, two write enables must be decoded from the WORD, nMWE and address line A0 (refer to
Figure 1-2). For writable 32-bit ROM/expansion banks, four write enables must be decoded from the same
signals plus the A1 address line. A byte write always causes a single bus cycle. Word writes to word-
aligned addresses are handled by the CL-PS7110, regardless of the width of the ROM/expansion bank.
Accesses to 8- or 16-bit-wide banks will cause multiple bus cycles (refer to Figure 1-3). Word writes to
non-word-aligned addresses normally cause a alignment fault. If the alignment fault check in the MMU is
not enabled, non-aligned work writes act as if both low address bits were zero.
May 1997
DATA BOOK v1.5
15
FUNCTIONAL DESCRIPTION
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