CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.9.2

LEDFLSH[5:2]

0011

0100

0101

0110

0111

Duty Ratio

(time on: time off)

04:12

05:11

06:10

07:09

08:08

LEDFLSH[5:2]

1011

1100

1101

1110

1111

Duty Ratio

(time on: time off)

12:04

13:03

14:02

15:01

16:00 (continually on)

Table 50. LED Duty Ratio (Continued)

SDCONF SDRAM Control Register (address 0x8000.2300)

31:11

Reserved

10

SDACTIVE

9

CLKCTL

8:7

SDWIDTH

6:5

SDSIZE

4:2

Reserved

1:0

CASLAT

Bit

1:0.

4:2.

6:5.

8:7.

9.

10.

31:11.

Description

How many clock cycles after CAS before the device is ready for reading or writing. . . ‘00’ =>

Reserved. . . , ‘01’ => Reserved, ‘10’ => CAS Latency = 2, ‘11’ => CAS Latency = 3. . . . . . . . . . .

The default value is ‘10’ for CAS latency = 2.

Reserved.

The capacity of each SDRAM. The values are: ‘00’=>16Mits, ‘01’=>64Mbits, ‘10’=>128Mbits,

‘11’=>256Mbits.

The width of each SDRAM. ‘00’=>4bits, ‘01’=>8bits, ‘10’=>16 bits, ‘11’=>32 bits.

Control over the SDRAM clock. ‘0’=> SDRAM clock is permanently enabled except when in

standby mode. ‘1’=>SDRAM clock stops when the CS89712 is put into inactive mode i.e.,

SDACTIVE = ‘0’, or when in standby mode.

Enables the SDRAM controller: ‘0’ disables, ‘1’ enables. The SDRAM controller will only initialize

if SDACTIVE is set to 1. After initialization, resetting this parameter will cause the SDRAM con-

troller to enter an inactive state. It will remain in this state until SDACTIVE is set to 1.

Reserved.

3.9.3 SDRFPR SDRAM Refresh Period Register (address 0x8000.2340)

31:16

Reserved

15:0

REFRATE

This 16-bit read/write register sets the interval between SDRAM refresh commands. The value programmed is the

interval in BLCK cycles e.g. for a 16 µs refresh period with a BCLK of 36 MHz, the following value should be used:

16x10-6 * 36x106 = 576

The refresh timer is set to 256 by nPOR to ensure a refresh time of better than 16 µs. This register should not be

programmed to a value below 2 otherwise the internal bus may become locked.

This register replaces DPFPR, which is no longer active. Writes to this register are ignored. Reads from this register

will produce unpredictable results.

96

DS502PP2

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