CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

Bit

19:24

25:29

30

31

Description

Pixel prescale: The pixel prescale field is a 6-bit field that sets the pixel rate prescale. The pixel

rate is always derived from a 36.864 MHz clock and is calculated from the formula:

Pixel rate (MHz) = 36.864 / (Pixel prescale + 1)

The pixel prescale value can be expressed in terms of the LCD size by the formula:

When the CS89712 is operating @ 18.432 MHz:

Pixel prescale = (36864000 / (Refresh Rate x Total pixels in display)) – 1

Refresh Rate is the screen refresh frequency (70 Hz to avoid flicker)

The value should be rounded down to the nearest whole number and zero is illegal and will result

in no pixel clock.

EXAMPLE: For a system being operated in the 18.432–73.728 MHz mode, with a 640 x 240

screen size, and 70 Hz screen refresh rate desired, the LCD Pixel prescale equals 36.864E6 /

(70 x 640x240) – 1 = 2.428

Rounding 2.428 down to the nearest whole number equals 2.

This gives an actual pixel rate of 36.864E6 / (2+1) = 12.288 MHz, which gives an actual refresh

frequency of 12.288E6 / (640x240) = 80 Hz.

Note: As the CL[2] low pulse time is doubled after every CL[1] high pulse this refresh frequency

is only an approximation, the accurate formula is 12.288E6 / ((640x240)+120) = 79.937 Hz.

AC prescale: The AC prescale field is a 5-bit number that sets the LCD AC bias frequency. This

frequency is the required AC bias frequency for a given manufacturer’s LCD plate. This fre-

quency is derived from the frequency of the line clock (CL[1]). The LCD M signal will toggle after

n+1 counts of the line clock (CL[1]) where n is the number programmed into the AC prescale

field. This number must be chosen to match the manufacturer’s recommendation. This is nor-

mally 13, but must not be exactly divisible by the number of lines in the display.

GSMD1: Grayscale mode bit number 1. Setting this bit enables 2 or 4 bits-per-pixel (01 or 11,

respectively) grayscaling. (Also see the GSMD2 bit definition.) Clearing this bit enables 1 bpp

(00) gray scaling only. Note: Gray scaling is always enabled when using the EP72xx LCD Con-

troller. Direct mapping of the frame buffer bits to the LCD display is not supported. However, this

can be accomplished by simply programming the palette register contents to correspond with the

frame buffer bit value (i.e., for 1 bpp (00) Direct mapping program the PALLSW register nibble

[3:0] with zeros, and nibble [7:4] with ones.)

GSMD2: Grayscale mode bit number 2. Setting this bit enables 4 bpp (11) gray scaling (15 gray

scales.) Clearing this bit enables 2 bits-per-pixel (01) gray scaling.

Table 55. LCDCON (Continued)

DS502PP2

101

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