CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

2.11 Memory and I/O Expansion Interface

Six separate linear memory or expansion segments

are decoded by the CS89712, two of which can be

reserved for two PC Cards, each interfacing to a

separate single CL-PS6700 device. Each segment

is 256 Mbytes in size. Two additional segments (in

addition to these six) are dedicated to the on-chip

SRAM and ROM. The on-chip ROM space is fully

decoded, and the SRAM space is decoded up to the

maximum size of the video frame buffer pro-

grammed in the LCDCON register (128 kbytes).

Beyond this address range the SRAM space is not

fully decoded (i.e., any accesses beyond 128 kbyte

range get wrapped around to within 128 kbyte

range). Any of the six segments are configured to

interface to a conventional SRAM-like interface,

and can be individually programmed to be 8-, 16-,

or 32-bits wide, to support page mode access, and

to execute from 1 to 8 wait states for non-sequential

accesses and 0 to 3 for burst mode accesses. The

zero wait state sequential access feature is designed

to support burst mode ROMs. For writable memory

devices which use the nMWE pin, zero wait state

sequential accesses are not permitted and one wait

state is the minimum which should be programmed

in the sequential field of the appropriate MEMCFG

register. Bus cycles can also be extended using the

EXPRDY input signal.

Page mode access is accomplished by setting

SQAEN = 1, enabling accesses of one random ad-

dress followed by three sequential addresses, etc.,

while keeping nCS asserted. These sequential

bursts can be up to four words long before nCS is

released to allow DMA and refreshes to take place.

This can significantly improve bus bandwidth to

devices such as ROMs which support page mode.

When SQAEN = 0, all accesses to memory are by

random access without nCS being de-asserted be-

tween accesses. Again nCS is de-asserted after four

consecutive accesses to allow DMA.

Bits 5 and 6 of the SYSCON2 register independent-

ly enable the interfaces to the CL-PS6700 (PC Card

slot drivers). When either of these interfaces are en-

abled, the corresponding chip select (nCS4 and/or

nCS5) becomes dedicated to that CL-PS6700 inter-

face. The state of SYSCON2 bit 5 determines the

function of chip select nCS4 (i.e., CL-PS6700 in-

terface or standard chip select functionality); bit 6

controls nCS5 in a similar way. There is no interac-

tion between these bits.

For applications that require a display buffer small-

er than 48k bytes, the on-chip SRAM can be used

as the frame buffer.

Before entering the Snooze State, the SRAM at

0x6000.0000 must be updated, under program con-

trol, with data to be displayed during the Snooze

State. In a system using the on-chip SRAM as the

frame buffer in normal operation, Snooze State can

be entered without requiring any data transfer first,

assuming data is stored in the on-chip SRAM in 1-

bit -per-pixel format.

The width of the boot device can be chosen by se-

lecting values of PE[1] and PE[0] during power on

reset. The inputs in Table 13 are latched by the ris-

ing edge of nPOR to select the boot option.

PE[1]

0

0

1

1

PE[0]

0

1

0

1

Boot Block

(nCS0)

32-bit

8-bit

16-bit

Undefined

Table 13. Boot Options

2.12 SDRAM Controller

The SDRAM controller provides all the connec-

tions to directly interface to up to two banks of

SDRAM, and the width of the memory interface is

programmable from 16 to 32 bits wide. Both banks

have to be of the same width. Each of the two banks

supported can be up to 256 Mbits in size. The sig-

DS502PP2

23

Share Link: