CS89712-CB View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS89712-CB Datasheet PDF : 170 Pages
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CS89712
ETHERNET TIMING CHARACTERISTICS
Parameter
Symbol Min
Typ
Max Unit
10BASE-T Receive
Allowable Received Jitter at Bit Cell Center
Allowable Received Jitter at Bit Cell Boundary
Carrier Sense Assertion Delay
Invalid Preamble Bits after Assertion of Carrier Sense
Carrier Sense Deassertion Delay
10BASE-T Link Integrity
tTRX1
-
-
±13.5 ns
tTRX2
-
-
±13.5 ns
tTRX3
-
540
-
ns
tTRX4
1
-
2
bits
tTRX5
-
270
-
ns
First Transmitted Link Pulse after Last Transmitted Packet
tLN1
Time Between Transmitted Link Pulses
tLN2
Width of Transmitted Link Pulses
tLN3
Minimum Received Link Pulse Separation
tLN4
Maximum Received Link Pulse Separation
tLN5
Last Receive Activity to Link Fail (Link Loss Timer)
tLN6
Ethernet EEPROM
8
16
24
ms
8
16
24
ms
60
100
200
ns
2
-
7
ms
25
-
150 ms
50
-
150 ms
EESK Setup time relative to EECS
EECS Setup time wrt ↑ EESK
EEDataOut Setup time wrt ↑ EESK
EEDataOut Hold time wrt ↑ EESK
EEDataIn Hold time wrt ↑ EESK
EECS Hold time wrt ↓ EESK
Min EECS Low time during programming
tSKS
100
-
tCCS
250
-
tDIS
250
-
tDIH
500
-
tDH
10
-
tCSH
100
-
tCS
1000
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
RXD±
tTRX1
tTRX3
Carrier Sense (internal)
tTRX4
tTRX2
Figure 34. 10BASE-T Receive
tTRX5
DS502PP2
159
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