CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.18.8 Buffer Configuration Register (BufCFG, address offset 10Ah)

7

RSVD

C

TxCol OvfloiE

6

SWint-X

B

Rx128iE

5:0

001011

A

RxMissiE

F

RxDestiE

9

TxUnder runtiE

E

8

Rdy4TxiE

D

Miss OvfloiE

Each bit in BufCFG enables an interrupt. The corresponding interrupt is enabled when set, and disabled when clear.

Bit

5:0

6

7

8

9

A

B

C

D

F

Description

001011: Identify this as register B, the Buffer Configuration Register.

SWint-X: When set, there is an interrupt requested by the software. The Ethernet port provides

the interrupt, and sets the SWint (Register C, BufEvent, Bit 6) bit. The Ethernet port acts upon

this command at once. SWint-X is an Act-Once bit. To generate another interrupt, rewrite a "1"

to this bit.

RSVD: Reserved; must be a “0” when writing to this register.

Rdy4TxiE: When set, there is an interrupt when the CS89712 is ready to accept a frame from

the software for transmission. (See Section 2.34, “Transmit Operation” for a description of the

transmit bid process.)

TxUnderruniE: When set, there is an interrupt if the CS89712 runs out of data before it

reaches the end of the frame (called a transmit underrun). When this happens, event bit

TXUnderrun (Register C, BufEvent, Bit 9) is set and the CS89712 makes no further attempts to

transmit that frame. If the software still wants to transmit that particular frame, the software

must go through the transmit request process again.

RxMissiE: When set, there is an interrupt if one or more received frames is lost due to slow

movement of receive data out of the receive buffer (called a receive miss). When this happens,

the RxMiss bit (Register C, BufEvent, Bit A) is set.

Rx128iE: When set, there is an interrupt after the first 128 bytes of a frame have been

received. This allows software to examine the Destination Address, Source Address, Length,

Sequence Number, and other information before the entire frame is received. This interrupt

should not be used with DMA. Thus, if either AutoRxDMA (Register 3, RxCFG, Bit A) or RxDM-

Aonly (Register 3, RxCFG, Bit 9) is set, the Rx128iE bit must be clear.

TxColOvfiE: If set, there is an interrupt when the TxCOL counter increments from 1FFh to

200h. (The TxCOL counter (Register 18) is incremented whenever the CS89712 sees that the

RXD+/RXD- pins (10BASE-T) go active while a packet is being transmitted.)

MissOvfloiE: If MissOvfloiE is set, there is an interrupt when the RxMISS counter increments

from 1FFh to 200h. (A receive miss is said to have occurred if packets are lost due to slow

movement of receive data out of the receive buffers. When this happens, the RxMiss bit (Reg-

ister C, BufEvent, Bit A) is set, and the RxMISS counter (Register 10) is incremented.)

RxDestiE: When set, there is an interrupt when a receive frame passes the Destination

Address filter criteria defined in the RxCTL register (Register 5). This bit provides an early indi-

cation of an incoming frame. It is earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE

is set, the BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent

changes from RxDest to Rx128.

Table 73. Buffer Configuration

After reset, if no EEPROM is found by the CS89712, then the register has the following initial state after reset. If an

EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the

EEPROM”.

Reset value is: 0000 0000 0000 1011

DS502PP2

123

Share Link: