CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

Bit

11

12

13

14

15

16-31

Description

LCNE: Left Channel Receive FIFO Not Empty (read-only)

0 — Left Channel Receive FIFO is empty

1 — Left Channel Receive FIFO is not empty

FIFO: FIFO Operation Completed (read-only)0 — A FIFO Operation has not completed since

the last time this bit was cleared1 — THe FIFO Operation was completed

Reserved

Reserved

Reserved

Reserved

Table 62. DAI Control, Data and Status Register Locations (Continued)

3.16.6.1 Right Channel Transmit FIFO Service Request Flag (RCTS)

The Right Channel Transmit FIFO Service Request Flag (RCTS) is a read-only bit which is set when

the Right Channel Transmit FIFO is nearly empty and requires service to prevent an underrun. RCTS

is set any time the Right Channel Transmit FIFO has four or fewer entries of valid data (half full or

less), and is cleared when it has five or more entries of valid data. When the RCTS bit is set, an in-

terrupt request is made unless the Right Channel Transmit FIFO interrupt request mask (RCTM) bit

is cleared. After the CPU fills the FIFO such that four or more locations are filled within the Right Chan-

nel Transmit FIFO, the RCTS flag (and the service request and / or interrupt) is automatically cleared.

3.16.6.2 Right Channel Receive FIFO Service Request Flag (RCRS)

The Right Channel Receive FIFO Service Request Flag (RCRS) is a read-only bit which is set when

the Right Channel Receive FIFO is nearly filled and requires service to prevent an overrun. RCRS is

set any time the Right Channel Receive FIFO has six or more entries of valid data (half full or more),

and cleared when it has five or fewer (less than half full) entries of data. When the RCRS bit is set,

an interrupt request is made unless the Right Channel Receive FIFO interrupt request mask (RCRM)

bit is cleared. After six or more entries are removed from the receive FIFO, the LCRS flag (and the

service request and / or interrupt) is automatically cleared.

3.16.6.3 Left Channel Transmit FIFO Service Request Flag (LCTS)

The Left Channel Transmit FIFO Service Request Flag (LCTS) is a read-only bit which is set when

the Left Channel Transmit FIFO is nearly empty and requires service to prevent an underrun. LCTS

is set any time the Left Channel Transmit FIFO has four or fewer entries of valid data (half full or less).

It is cleared when it has five or more entries of valid data. When the LCTS bit is set, an interrupt re-

quest is made unless the Left Channel Transmit FIFO interrupt request mask (LCTM) bit is cleared.

After the CPU fills the FIFO such that four or more locations are filled within the Left Channel Transmit

FIFO, the LCTS flag (and the service request and / or interrupt) is automatically cleared.

3.16.6.4 Left Channel Receive FIFO Service Request Flag (LCRS)

The Left Channel Receive FIFO Service Request Flag (LCRS) is a read-only bit which is set when

the Left Channel Receive FIFO is nearly filled and requires service to prevent an overrun. LCRS is

set any time the Left Channel Receive FIFO has six or more entries of valid data (half full or more),

and cleared when it has five or fewer (less than half full) entries of data. When the LCRS bit is set, an

interrupt request is made unless the Left Channel Receive FIFO interrupt request mask (LCRM) bit

is cleared. After six or more entries are removed from the receive FIFO, the LCRS flag (and the ser-

DS502PP2

113

Share Link: