V96SSC-33LPB1 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
V96SSC-33LPB1
QuickLogic Corporation
V96SSC-33LPB1 Datasheet PDF : 20 Pages
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V96SSC
Table 13: Memory Interface Signals
#
Sym-
bol
Description
1 tARA Address input valid to row address valid on MA[11:0]
2 tRAH Row address hold after CLK2
3 tCAV CLK2 to column address valid
4 tCAH Column address hold after CLK2 or CLK2
5
tBCAH
Column address hold after CLK2 or CLK2 during burst
operation
6
tBCAV
CLK2 or CLK2 to column address valid during burst
operation
7 tDRAH DRAM row address hold
8 tDCAH DRAM column address hold
9 tRSHL CLK2 to RAS asserted delay
10 tRSLH CLK2 to RAS de-asserted delay
11 tCHL1 CLK2 to CAS asserted delay
12 tCLH1 CLK2 to CAS de-asserted delay
13 tCHL2 CLK2 to CAS asserted delay
14 tCLH2 CLK2 to CAS de-asserted delay
15 tOEHL CLK2 to OE asserted delay
16 tOELH CLK2 to OE de-asserted delay
17 tWEHL CLK2 to WE asserted delay
18 tWELH CLK2 to WE de-asserted delay
19 tLEHL1 CAS asserted to LE asserted delay (read)
20 tLELH1 CAS de-asserted to LE de-asserted (read)
21 tLEHL2 CAS asserted to LE de-asserted delay (write)
22 tLELH2 CAS de-asserted to LE asserted (write)
33 MHz
Notes Min Max Units
1
13 ns
3
ns
1
12 ns
1,2 4
ns
1,2 4
ns
1,2
14 ns
3 tM+1
ns
4 tN+1
ns
1
9 ns
1
9 ns
1
11 ns
1
10 ns
1,5
10 ns
1,6
10 ns
1
10 ns
1
9 ns
1
10 ns
1
10 ns
1
1 ns
1
1 ns
1,7
1 ns
1,7
1 ns
Copyright © 1997, V3 Semiconductor Inc.
V96SSC Data Sheet Rev 2.3
19
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