V96SSC-33LPB1 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
V96SSC-33LPB1
QuickLogic Corporation
V96SSC-33LPB1 Datasheet PDF : 20 Pages
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V96SSC
Table 11: Clock, ALE, Synchronous Inputs and Outputs
33 MHz
# Symbol
Description
Notes Min Max Units
1
tC CLK2 period
15
ns
2 tCH CLK2 high time
6
ns
3
tCL CLK2 low time
6
ns
4 tSU Synchronous input setup
10
ns
5
tH Synchronous input hold
3
ns
6 tCO CLK2 to synchronous output delay
1
12 ns
7 tALE ALE pulse width
tC-7
ns
8 tASU Address setup to ALE falling
3
ns
9 tAH Address hold from ALE falling
1
ns
Notes:
1. tCO is for signals RSTOUT, HOLD, DACKx, and INT.
Figure 6: Internal Register Read/Write Waveforms
CLK2
CLK
ADS
A31,A[26:23]
AD[15:0]
W/R
BLAST
READY
IOC
ADDRESS VALID
ADDRESS VALID
tAD0
tADH
tSU
ADDR
,,,DATA IN
tADV ,,,
ADDR ,,,,, DATA OUT
,,,,,
tH
tRZL
tRLH
tRHZ
OPORT
tOCHL
OPORT
Copyright © 1997, V3 Semiconductor Inc.
V96SSC Data Sheet Rev 2.3
17
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