SST89E564-40-C-PI View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
MFG CO.
SST89E564-40-C-PI Datasheet PDF : 58 Pages
| |||
FlashFlex51 MCU
SST89E564 / SST89V564 / SST89E554 / SST89V554
Preliminary Specifications
8.0 SECURITY LOCK
The Security Lock protects against software piracy and
prevents the contents of the flash from being read by unau-
thorized parties. It also protects against code corruption
resulting from accidental erasing and programming to the
internal flash memory. There are two different types of
security locks in the device security lock system: Hard Lock
and SoftLock.
8.1 Hard Lock
When Hard Lock is activated, MOVC or IAP instructions
executed from an unlocked or SoftLocked program
address space, are disabled from reading code bytes in
Hard Locked memory blocks (See Table 8-2). Hard Lock
can either lock both flash memory blocks or just lock the 8
KByte flash memory block (Block 1). All External Host and
IAP commands except for Chip-Erase are ignored for
memory blocks that are Hard Locked.
8.2 SoftLock
SoftLock allows flash contents to be altered under a secure
environment. This lock option allows the user to update
program code in the SoftLocked memory block through In-
Application Programming Mode under a predetermined
secure environment. For example, if Block 1 (8K) memory
block is locked (Hard Locked or SoftLocked), and Block 0
(64K for SST89E564/SST89V564) memory block is Soft-
Locked, code residing in Block 1 can program Block 0. The
following IAP mode commands issued through the com-
mand mailbox register, SFCM, executed from a Locked
(Hard Locked or SoftLocked) block, can be operated on a
SoftLocked block: Block-Erase, Sector-Erase, Byte-Pro-
gram and Byte-Verify.
In External Host Mode, SoftLock behaves the same as a
Hard Lock.
8.3 Security Lock Status
The three bits that indicate the device security lock
status are located in SFST[7:5]. As shown in Figure 8-
1 and Table 8-1, the three security lock bits control the
lock status of the primary and secondary blocks of
memory. There are four distinct levels of security lock
status. In the first level, none of the security lock bits
are programmed and both blocks are unlocked. In the
second level, although both blocks are now locked and
cannot be programmed, they are available for read
operation via Byte-Verify. In the third level, three differ-
ent options are available: Block 1 Hard Lock / Block 0
SoftLock, SoftLock on both blocks, and Hard Lock on
both blocks. Locking both blocks is the same as Level
2 except read operation isn’t available. The fourth level
of security is the most secure level. It doesn’t allow
read/program of internal memory or boot from external
memory. Please note that for unused combinations of
the security lock bits, the chip will default to Level 4
status. For details on how to program the security lock
bits refer to the External Host Mode and In-Application
Programming Section.
UUU/NN
PUU/SS
Level 1
Level 2
UPU/SS
UPP/LL
PPU/LS
UUP/LS
Level 3
PUP/LL
UPP/LL
PPP/LL
Level 4
FIGURE 8-1: SECURITY LOCK LEVELS
384 ILL F38.2
Notes: P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1), N = Not Locked, L = Hard Locked, S = SoftLocked.
©2001 Silicon Storage Technology, Inc.
40
S71181-03-000 9/01 384
Share Link: 