FlashFlex51 MCU
SST89E564 / SST89V564 / SST89E554 / SST89V554
Preliminary Specifications
SCK Cycle #
(for reference)
SCK (CPOL=0)
1
2
3
4
5
6
7
8
SCK (CPOL=1)
MOSI
(from Master)
MISO
(from Slave)
SS# (to Slave)
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
*
* Not defined, but normally MSB of next received byte
384 ILL F54.1
FIGURE 6-2: SPI TRANSFER FORMAT WITH CPHA = 0
SCK Cycle #
(for reference)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(from Master)
MISO
(from Slave)
SS# (to Slave)
1
2
3
4
5
6
7
MSB 6
5
4
3
2
1
* MSB 6
5
4
3
2
1
* Not defined but normally LSB of previously transmitted character
8
LSB
LSB
384 ILL F55.1
FIGURE 6-3: SPI TRANSFER FORMAT WITH CPHA = 1
©2001 Silicon Storage Technology, Inc.
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