CS7654 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS7654 Datasheet PDF : 62 Pages
| |||
CS7654
I2C Serial Control
SDAS - Primary I2C Data Bus, PIN 35.
Primary I2C data bus. Used with SCL to read and write the internal register set.
SCLS - Primary I2C Clock, PIN 36.
Primary I2C Clock. Used with SDA to read and write the internal register set.
SDAM - Secondary I2C Data Bus, PIN 17.
Secondary I2C data bus with limited bus mastering capabilities. Used with SCLSEC to read and
write I2C devices located on the secondary bus. Various devices can be isolated by the CS7654
from the primary I2C bus. The CS7654 will start reading I2C EPROM devices at addresses A0h
after RESET. It will download the EPROM contents into the specified registers inside the
secondary bus devices as well as any CS7654 registers specified in the EPROM entries.
Devices are typically connected to either the primary or the secondary I2C bus. However, the
two busses may be connected together when system design requires the use of EPROM
initialization while at the same allowing direct access to all the camera devices from the
external I2C controller.
SCLM - Secondary I2C Clock, PIN 18.
Secondary I2C clock with limited bus mastering capabilities. Used with SDASEC to read and
write I2C devices located on the secondary bus. Various devices can be isolated by the CS7654
from the primary I2C bus. The CS7654 will start reading I2C EPROM devices at addresses A0h
after RESET, and download the EPROM contents into the specified secondary bus registers, as
well as any CS7654 registers specified in the EPROM entries. Devices are typically connected
to either the primary or the secondary I2C bus. However, the two busses may be connected
together when system design requires the use of EPROM initialization while at the same time
allowing direct access to all the camera devices from the external I2C controller.
P4BYTMODE - Four-byte Mode I2C Operation Enable, PIN 46.
Places CS7654 in the Four-byte mode for I2C transactions on the primary I2C bus. Active high.
Digital Video Outputs and Clocking
DOUT[9:0] - Channel Digital Output Bits, Pins [28:19].
CMOS level 10-bit digital video output channel "A." Either YCrCb interleaved digital video
output data, or Y component digital video data is available at this port according to the state of
bit 5 in register 06h at SA 0x34h.
HIZEN - Output enable, PIN 44.
CMOS level digital input pin to place all digital video output in HI-Z mode. This pin works in
conjunction with OE bit in register 06h at SA 0x34h. To disable/power down DAC see registers
description 0x04h and 0x05h at SA 0x00h.
57
Share Link: 